roy
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17 - the trick here is to spread your operations across as many registers as you can, and reduce interdependence of ops that follow each other immediately in the instruction pipeline. You get 6 cycles (5 ops) -- the minimum as it implies only one such dependence --if, for example u arrange the ops as follows:
1) R0*R1->R3 (1 cycle)
2) R1*R2->R5 (1 cycle)
3) R2*R3->R4 (1 cycle)
4) R3+R5->R6 (2 cycles -- the next op depends on output)
5) R4+R6->R7 (1 cycle)
18 - similar to above
20 - both arrays fit the cache so only the values of A will have to be written to memory
21 - same logic adapted to write-back
33 - plot graphical representation s of both procs
34 - attach probability to each path. E.g.,
probability of U->V->Y is 1/4
U->V->X->Y is 1/12
etc.
Now, the probability of returning (once!) back to U is
(1/2+1/4)*2/3=1/2
hence the mathematical expectation of the number of returns back to U is 1/2+1/4+... = 1
Adding the initial execution of U we get 1+1=2
36 - reverse the circuit logic because then you will have fewer options: the output is 1 only when the input is 2, 3 and 7. Then negate the resulting simple expression and get the result. That is much easier than substitution.
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Computer Science Test (Read 1562 times)
